HV2303 features hvcmos technology for high performance integrated bleed resistors on the outputs 3.3v or 5.0v cmos input logic level 20mhz data shift clock frequency very low quiescent power dissipation - 10a low parasitic capacitance dc to 10mhz analog signal frequency -60db typical off-isolation at 5.0mhz cmos logic circuitry for low power excellent noise immunity cascadable serial data register with latches flexible operating supply voltages applications medical ultrasound imaging ndt metal ? aw detection piezoelectric transducer drivers inkjet printer heads optical mems modules ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex HV2303 is a low charge injection 8-channel high voltage analog switch integrated circuit (ic) with bleed resistors. the device can be used in applications requiring high voltage switching controlled by low voltage signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. data is input into an 8-bit shift register that can then be retained in an 8-bit latch. to reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. data is clocked in during the rising edge of the clock. using hvcmos technology, this device combines high voltage bilateral dmos switches and low power cmos logic to provide ef? cient control of high voltage analog signals. the device is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +40v/-140v, +90v/-90v, and +140v/-40v. block diagram low charge injection, 8-channel high voltage analog switch with bleed resistors level shifters & charge control vnn vpp d le clr sw0 d le clr d le clr d le clr d le clr latches output switches le clr vdd gnd sw1 sw2 sw6 sw7 rgnd clk 8-bit shift register d in d out
2 HV2303 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. parameter value v dd logic supply -0.5v to +7.0v v pp -v nn differential supply 200v v pp positive supply -0.5v to v nn +200v v nn negative supply +0.5v to -180v logic input voltage -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 1.0a storage temperature -65c to 150c thermal resistance ( ja ): 48-lead lqfp (fg) 61 o c/w operating conditions sym parameter value v dd logic power supply voltage 3.0v to 5.5v v pp positive high voltage supply 40v to v nn +180v v nn negative high voltage supply -40v to -140v v ih high level input voltage 0.9v dd to v dd v il low-level input voltage 0v to 0.1v dd v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v t a operating free air temperature 0 o c to 70 o c notes: 1. power up/down sequence is arbitrary except gnd must be powered-up ? rst and powered down last. 2. v sig must be v nn v sig v pp or ? oating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. product marking yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packaging *may be part of top marking top marking bottom marking yyww HV2303fg lllllllll cccccccc aaa yy = year sealed ww = week sealed l = lot number c = country of origin a = assembler id* = green packaging *may be part of top marking top marking bottom marking yyww HV2303pj llllllllll ccccccccccc aaa 48-lead lqfp (fg) 28-lead plcc (pj) pin con? gurations 48-lead lqfp (fg) 28-lead plcc (pj) 1 48 1 28 4 26 ordering information device package options 48-lead lqfp 7x7mm body, 1.6mm height (max), 0.50mm pitch 28-lead plcc .453x.453in body, .180in height (max.), .050in pitch HV2303 HV2303fg-g HV2303pj-g -g indicates package is rohs compliant (green)
3 HV2303 dc electrical characteristics (over operating conditions unless otherwise speci? ed ) r ons small signal switch on-resistance ---50--- i sig = 5.0ma v pp = +40v v nn = -120v ---42--- i sig = 200ma ---40--- i sig = 5.0ma v pp = +80v v nn = -80v ---32--- i sig = 200ma ---38--- i sig = 5.0ma v pp = +120v v nn = -40v ---29--- i sig = 200ma r ons small signal switch on-resistance matching - - - 5.0 - - - % i sig = 5.0ma, v pp = +80v, v nn = -80v r onl large signal switch on-resistance ---30---v sig = v pp -10v, i sig = 0.5a r int value of output bleed resis- tance - - 20 35 50 - - k output switch to rgnd i rint = 0.5ma i sol switch off leakage per switch - 5.0 - 1.0 10 - 15 a v sig = v pp -10v, v nn +10v v os dc offset switch off - 300 - 100 300 - 300 mv no load dc offset switch on - 500 - 100 500 - 500 mv i ppq quiescent v pp supply current - - - 10 50 - - a all switches off i nnq quiescent v nn supply current - - - -10 -50 - - a all switches off i ppq quiescent v pp supply current - - - 10 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - -10 -50 - - a all switches on, i sw = 5.0ma i sw switch output peak current - - - - 1.0 - - a v sig duty cycle <0.1%, 1.0s f sw output switching frequency - - - - 50 - - khz duty cycle = 50% i pp average v pp supply current - - 1.0 1.2 1.5 - - ma v pp = +40v v nn = -120v all output switches are turning on and off at 50khz with no load - - 1.0 1.2 1.5 - - v pp = +80v v nn = -80v - - 1.0 1.2 1.5 - - v pp = +120v v nn = -40v i nn average v nn supply current - - 1.0 1.2 1.5 - - ma v pp = +40v v nn = -120v - - 1.0 1.2 1.5 - - v pp = +80v v nn = -80v - - 1.0 1.2 1.5 - - v pp = +120v v nn = -40v i dd average v dd supply current - 4.0 - - 4.0 - 4.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq quiescent v dd supply current - 10 - - 10 - 10 a all logic inputs are static i sor data out source current 0.45 - 0.45 0.70 - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 0.70 - 0.40 - ma v out = 0.7v c in logic input capacitance - 10 - - 10 - 10 pf --- sym parameter 0 o c+25 o c+70 o c units conditions min max min typ max min max
4 HV2303 ac electrical characteristics (over recommended operating conditions: v dd = 5.0v, t r = t f 5ns, 50% duty cycle, c load = 20pf unless otherwise speci? ed) t sd set up time before le rises 25 - 25 - - 25 - ns --- t wle time width of le 56 - - 56 - 56 - ns v dd = 3.0v 12 - - 12 - 12 - v dd = 5.0v t do clock delay time to data out 50 100 50 78 100 50 100 ns v dd = 3.0v 15 40 15 30 40 15 40 v dd = 5.0v t wcl time width of clr 55 - 55 - - 55 - ns --- t su set up time data to clock 21 - - 21 - 21 - ns v dd = 3.0v 7.0 - - 7.0 - 7.0 - v dd = 5.0v t h hold time data from clock 2.0 - 2.0 - - 2.0 - ns v dd = 3.0 or 5.0v f clk clock frequency - 8.0 - - 8.0 - 8.0 mhz v dd = 3.0v - 20 - - 20 - 20 v dd = 5.0v t r , t f clock rise and fall times - 50 - 50 - 50 ns --- t on turn on time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k t off turn off time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k dv/dt maximum v sig slew rate -20- -20-20 v/ns v pp = +40v, v nn = -120v - 20 - - 20 - 20 v pp = +80v, v nn = -80v - 20 - - 20 - 20 v pp = +120v, v nn = -40v k o off isolation -30 - -30 -33 - -30 - db f = 5.0mhz, 1k/15pf load -58 - -58 - - -58 - f = 5.0mhz, 50 load k cr switch crosstalk -60 - -60 -70 - -60 - db f = 5.0mhz, 50 load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width, 2.0% duty cycle c sg(off) off capacitance sw to gnd - - - 6.5 - - - pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd - - - 21.7 - - - pf 0v, f = 1.0mhz +v spk output voltage spike ---18--- mv v pp = +40v, v nn = -120v, r load = 50 -v spk ---60--- +v spk ---30--- v pp = +80v, v nn = -80v, r load = 50 -v spk ---60--- +v spk ---33--- v pp = +120v, v nn = -40v, r load = 50 -v spk ---60--- qc charge injection ---270--- pc v pp = +40v, v nn = -120v, v sig = 0v - - - 220 - - - v pp = +80v, v nn = -80v, v sig = 0v - - - 152 - - - v pp = +120v, v nn = -40v, v sig = 0v sym parameter 0 o c+25 o c+70 o c units conditions min max min typ max min max
5 HV2303 truth table d0 d1 d2 d3 d4 d5 d6 d7 le clr sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 llloff hllon llloff hllon llloff hllon llloff hllon lll off hll on lll off hll on lll off hll on lll off hll on x x x x x x x x h l hold previous state x x x x x x x x x h all switches off notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register da ta ? ow through the latch. 4. d out is high when data in the shift register 7 is high. 5. shift register clocking has no effect on the switch states if le is high. 6. the clr clear input overrides all other inputs.
6 HV2303 test circuits pp v pp -10v pp pp pp pp pp pp pp v pp -10v vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd vpp vdd vnn rgnd gnd
7 HV2303 pin # pin name pin # pin name 1 sw5 25 v nn 2nc26nc 3 sw4 27 rgnd 4nc28gnd 5 sw4 29 v dd 6nc30nc 7nc31nc 8 sw3 32 nc 9nc33d in 10 sw3 34 clk 11 nc 35 le 12 sw2 36 clr 13 nc 37 d out 14 sw2 38 nc 15 nc 39 sw7 16 sw1 40 nc 17 nc 41 sw7 18 sw1 42 nc 19 nc 43 sw6 20 sw0 44 nc 21 nc 45 sw6 22 sw0 46 nc 23 nc 47 sw5 24 v pp 48 nc pin con? guration - 48-lead lqfp (fg) pin con? guration - 28-lead plcc (pj) pin # pin name pin # pin name 1sw315nc 2 sw3 16 d in 3 sw2 17 clk 4sw218 le 5 sw1 19 clr 6 sw1 20 d out 7 sw0 21 sw7 8 sw0 22 sw7 9nc23sw6 10 v pp 24 sw6 11 rgnd 25 sw5 12 v nn 26 sw5 13 gnd 27 sw4 14 v dd 28 sw4 typical waveforms data in le clock data out off on (typ ) vout 50% 50% 50% 50% t wle t sd t su t h 50% 50% t off 50% t do t on t wcl clr d n+1 d n d n-1 50% 50% 90% 10%
8 HV2303 48-lead lqfp package outline (fg) 7x7mm body, 1.6mm height (max.), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80 6.80 8.80 6.80 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20 7.20 9.20 7.20 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not speci? ed in the original jedec drawing. the value listed is for reference only. drawings are not to scale. 1 seating plane gauge plane l l1 l2 view b view b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) 48 note 1: a pin 1 identi? er must be located in the index area indicated. the pin 1 identi? er may be either a mold, or an embedded metal or marked feature.
9 HV2303 (the package drawing (s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp - HV2303 nr042308 28-lead plcc package outline (pj) .453x.453in body, .180in height (max.), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .485 .450 .485 .450 .050 bsc nom .172 .105 - - - .490 .453 .490 .453 max .180 .120 .083 .021 .032 .495 .456 .495 .456 jedec registration ms-018, variation ab, issue a, june, 1993. drawings not to scale . note 1: a pin 1 identi? er must be located in the index area indicated.the pin 1 identi? er may be either a mold, or an embedded metal or marked feature. .150 max .048/.042 x 45 o 1 .075 max 4 26 d d1 e1 e top view side view view b a a2 a1 seating plane e note 1 (index area) .056/.042 x 45 o .020 max 3 places base plane .020 min 28 b view b b1
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